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description the IR3Y48A1 is a cmos single-chip signal processing ic for ccd area sensors which includes correlated double sampling circuit (cds), clamp circuit, programmable gain amplifier (pga), reference voltage generator, black level detection circuit, 18 mhz 10-bit analog-to-digital converter (adc), timing generator for internally required pulses, and serial interface for internal function control and pga gain control. features ? low power consumption : 80 mw (typ.) ? wide gain range : C1.94 to 36 db (gain step : 0.047 db/step) ? high speed sample-and-hold circuits : pulse width 11 ns (min.) ? independent cds and pga gain control C cds : C1.94/0/6/12 db C pga : 0 to 24 db ? black level canceler C settling target : 16 to 127 lsb ? capable of independent input of adc conversion clock and data output clock ? power down mode : less than 1 mw ? built-in serial interface ? 10-bit adc operating up to 18 mhz C dnl : 0.6 lsb (typ.) ? maximum input level of ccd signals : 1.1 vp-p ? accepts a direct signal input to adc or pga (input level : 1.0 vp-p (typ.)) ? single 2.7 to 3.6 v power supply ? package : 48-pin qfp * (p-qfp048-0707) 0.5 mm pin-pitch * contact sharp in order to obtain the details of package dimensions of the IR3Y48A1. pin connections IR3Y48A1 1 IR3Y48A1 ccd signal process & digital interface ic 1 48 47 46 45 44 43 42 41 40 39 37 13 14 15 16 17 18 19 20 21 22 23 24 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 nc av dd4 nc v rn v rp av dd2 av dd2 av ss2 av ss2 v com ccdin refin outck resetn av dd3 av ss3 stbyn csn sdata sck obp ccdclp blk adclp clpcap adin obcap monout nc aiset av dd1 av ss1 nc adck shr shd do 9 do 8 do 7 do 6 do 5 dv dd dv ss do 4 do 3 do 2 do 1 do 0 38 48-pin qfp top view (p-qfp048-0707) in the absence of confirmation by device specification sheets, sharp takes no responsibility for any defects that may occur in equipment using any sharp devices shown in catalogs, data books, etc. contact sharp in order to obtain the latest device specification sheets before using any sharp devic e. back
IR3Y48A1 2 block diagram 13 12 ccd adin adclp ccdclp C1.94/0/6/12 db s/h obcap aiset adck 11 14 15 18 22 26 28 27 25 31 29 30 36 35 32 blk obp ccdclp timing generator serial register black level register compare 10-bit adc obp 0 to 6 db (0.047 db/step) 0/6/12/18 db pga rough pga fine dac adclp csn sck sdata outck resetn stbyn 42 43 33 20 2 34 19 4 10 5 6,7 8,9 dv ss dv dd av ss3 av ss2 av ss1 av dd4 av dd3 av dd2 av dd1 v rn v com bandgap v ref v rp do 0 to do 9 37 to 41, 44 to 48 monout 16 shd 24 shr clpcap dc refin ccdin clamp clpcap 23 cds +
IR3Y48A1 3 pin description 1nc C no connection. pin no. symbol i/o equivalent circuit description supply of 2.7 to 3.6 v analog power. C av dd4 2 3 nc C no connection. v dd gnd ? adc internal negative reference voltage. (connect to av ss via 0.1 f.) o v rn 4 supply of 2.7 to 3.6 v analog power. C av dd2 6 5 v rp o 9 av ss2 C an analog grounding pin. 8 av ss2 C an analog grounding pin. 7 av dd2 C supply of 2.7 to 3.6 v analog power. adc internal common reference voltage. (connect to av ss via 0.1 f.) o v com 10 11 ccdin i cds circuit data input. i refin 12 adc internal positive reference voltage. (connect to av ss via 0.1 f.) cds circuit reference input. v dd gnd ? 10 v dd gnd ? clamp level output. (connect to av ss via 0.1 f.) o clpcap 13 14 15 16 ? internal fet gate adin obcap monout i o o adin signal input. black level integration voltage. (connect to av ss via 0.1 f.) monitor output of cds or pga. v dd gnd ?
IR3Y48A1 4 pin no. symbol i/o equivalent circuit description C nc 17 no connection. internal analog circuit bias current input. (connect to av ss via 4.7 k$.) 18 aiset * i no connection. 21 nc C an analog grounding pin. 33 av ss3 C an analog grounding pin. 20 av ss1 C supply of 2.7 to 3.6 v analog power. 19 av dd1 C i adck 22 adc sampling clock input. reference sampling pulse input. data sampling pulse input. pulse input for adin clamp and black calibration control. blanking pulse input. clamp control input. black level period pulse input. serial port clock input. serial port data input. serial port chip selection (active at low). power down control (power down at low). 23 24 25 26 27 28 29 30 31 32 shr shd adclp blk ccdclp obp sck sdata csn stbyn i i i i i i i i i i C av dd3 34 supply of 2.7 to 3.6 v analog power. v dd gnd ? 18 v dd gnd * high-z at power down ? internal fet gate clock input for adc output. 36 outck i reset signal input (reset at low). 35 resetn i v dd gnd
IR3Y48A1 5 pin no. symbol i/o equivalent circuit description o do 0 * 37 adc digital output (3 state) (lsb). v dd gnd 41 do 4 * o adc digital output (3 state). 40 do 3 * o adc digital output (3 state). 39 do 2 * o adc digital output (3 state). 38 do 1 * o adc digital output (3 state). 43 dv dd C supply of 2.7 to 3.6 v digital power. 42 dv ss C a digital grounding pin. adc digital output (3 state) (msb). o do 9 * 48 adc digital output (3 state). o do 8 * 47 adc digital output (3 state). o do 7 * 46 adc digital output (3 state). o do 6 * 45 adc digital output (3 state). o do 5 * 44 v dd gnd * high-z at power down note : nc pins are not connected internally, but recommended to be connected to av ss .
IR3Y48A1 6 functional description outline the configuration of the IR3Y48A1 is described below. shr shd monout outck v ref clamp cds refin ccdin adin adck blk obp ccdclp adclp csn sdata sck ccd pga do 0 to do 9 black control serial register timing generator IR3Y48A1 + 10-bit adc ccd ob effective pixel (ob) blanking adck blk obp ccdclp data output black code do 0 -do 9 outck general timing note : in this chart, the cycles of the obp and ccdclp show the same timing. but the obp and ccdclp can be input at different timing.
IR3Y48A1 7 reference clock (shr) data clock (shd) refin ccdin ccd cds cds output = v (cds) = v (data) C v (precharge) reset pulse reset pulse v (precharge) v (data) max. level shr shr shd shd sig f smax = 18 mhz / t smin = 55 ns sig v (cds) cds operation cds circuit cds (correlated double sampling) circuit connect the signal from a ccd sensor to the ccdin pin via a capacitor and connect the refin pin to av ss via a capacitor. the cds circuit holds the ccd precharge (reference) level at shr pulse, then it samples the ccd pixel data at shd pulse. correlated (common) noise is removed by the subtracting precharge level from the pixel data level. cds can choose a gain setting from 0, 6.02, 12 or C1.94 db (mode (3) register d 4 & d 5 bits). a cds gain is controlled separately from a pga gain. to reduce noise as much as possible, it is recommended to increase the cds gain first before increasing the pga gain.
IR3Y48A1 8 clamp circuits dc clamp dc level of the ccdin/refin input is fixed by internal dc clamp circuit. dc level of c-coupled ccd signal at the cds input is set to clpcap by the internal dc clamp circuit. normally clamp switches are turned on at the black level calibration period. place 0.1 f external capacitance between clpcap and av ss . timing control (register conditions) refin ccdin ccd shr shd ccdclp clamp source clpcap dc clamp function (ccdclp) clpcap ccdclp adck ccd clpcap level refin, ccdin clamp level clamp timing dc clamp note : for adin input, clamp operation is controlled by adclp. (black level calibration is performed at the same time.) clamp of the adin signal clamp operation for the adin path is also available. note that clamp voltage [clpcap] is different between ccdin/refin input and the adin input. clamp operation of adin signal can be turned off by register setting. clamp circuit is controlled by adclp signal at "adin signal to adc" mode. black level calibration circuit is also controlled by adclp at "adin signal to pga" mode. clamp control following items are selectable by the register setting. a) clamp current [mode (2) register d 7 ] normal or fast clamp is selectable for charge current. (select normal clamp in general.) b) clamp target [mode (2) register d 5 & d 4 ] input signals (refin and ccdin) to be clamped are selectable. it is also possible to turn off the clamp function. adclp adin to pga or to adc timing control clpcap (adclp) adin dc clamp function adin dc clamp
IR3Y48A1 9 cds refin s/h ccdin adin (path for adin) adclp adclp obp obp compare black level register obcap rough fine do 0 to do 9 pga pga + dac 10-bit adc black level calibration ccd adck obp obcap previous black level blanking blanking effective pixel signal effective pixel signal optical black period resulting black calibration level (hold) black level calibration timing black level cancel circuit the purpose of a black level cancel circuit is to control the dc level of the pga input so that the adc output code at a optical black period may correspond to the black level code set up by the register. the black level code of (1 to) 16 to 127 lsb (default : 64 lsb) is available. a black level cancel loop is established while the obp pin is active. in this loop, the adc output code is compared with the black level code and the voltage of the obcap capacitor is controlled by the result. thus, the obcap voltage settles gradually, and the signal level of the optical black period corresponds to the established value. the charge of the obcap capacitor is reset under following conditions : q set the black level reset register to "1". [mode (1) register d 1 = 1] w set the reset pin to low. e power down (by the stbyn pin or register control) the dc clamping [ccdclp] is allowed while the obp pin is low. the black level cancellation is also available in "adin signal to pga" mode. (see the broken line path of " black level calibration " below.) the black level cancellation is available at the adclp period in this mode. (that means a clamping and a black level cancelling are done simultaneously.)
IR3Y48A1 10 high-speed black level cancellation the IR3Y48A1 has the function that settles a black level at high speed. the function that increases a settling speed in a fixed period from the access to the serial interface can become available by the register setting. this function increases the gain of the settling dac in a fixed period, and it increases the charge/discharge current to the obcap capacitor. the black level boost function is set with the mode (3) register, d 3 , d 2 , d 1 and d 0 bits. the default setting is always low gain (d 3 = d 2 = d 1 = d 0 = 0). by setting the register d 2 , d 1 and d 0 bits, the gain becomes high during 1 to 7 times of obp pulse period after any access to the serial interface. after that period, the gain returns to low. when setting d 3 to "1", the gain is always high. the csn signal becomes the starting point of the obp pulse count. the right figure of "black loop settling gain boost timing" is the timing chart when the boost control is on and the boost period is set to 3. the left figure of "black level settling" below is the image of the settlement when the gain is high or low. csn csn obp obp dout black code black offset black offset high gain low gain black level target value area ccd (change register value) black level settling t sucs csn obp counter black loop gain 0 high gain gain boost function on (mode (3) d 3 = 1) high gain for 3 pulses (mode (3) d 2 = 0, d 1 = 1, d 0 = 1) high gain low gain 123 0 312012 t hcs black loop settling gain boost timing + cds obcap pga d 0 to d 9 10-bit adc compare black level register dac i dac low gain : small high gain : large obp + black level boost parameter symbol conditions typ. csn setup time 0 min. s unit max. t sucs t hcs clock 5 csn hold time csn & obp timing
IR3Y48A1 11 gain control circuit the total gain for a ccd input signal covers from C1.94 to +36 db. this range consists of cds (0/6/12/C1.94 db), pga rough (0/6/12/18 db), and pga fine (0 to 6 db (0.047 db/step)). the cds gain is controlled by a 2-bit register and the pga gain is controlled by a 9- bit register. mode (3) register (d 5 & d 4 ) 0/6/12/C1.94 db ccdin adin (pgain) rough (0/6/12/18 db) pga gain cds gain fine 0.047 db/step (0 to 6 db) to adc total gain = C1.94 to +35.91 db 000 0 db 24 db 0.047 db 1 step 511 (decimal) pga gain control total gain pga gain setting total gain cds gain = 12 db (d 5 = 1, d 4 = 0) cds gain = 6 db (d 5 = 0, d 4 = 1) cds gain = 0 db (d 5 = 0, d 4 = 0) cds gain = C1.94 db (d 5 = 1, d 4 = 1) 36 db C1.94 db 000 511 (decimal) 30 db 24 db 18 db 12 db 6 db 0 db gain control note : ? the gain of the adin (pga) input pass can be set from 0 to 24 db.
IR3Y48A1 12 a/d converter circuit the IR3Y48A1 integrates an 18 mhz 10-bit full pipeline a/d converter (adc). this adc converts following signals : 1. the signal from the ccdin input through a cds and a pga 2. the signal from the adin input through a pga at the adin (pga input) mode. 3. the signal from the adin input at the adin (adc input) mode. a/d conversion range the analog input range of the adc is determined by the internal reference voltage. the full scale of the adc is 1.0 vp-p (single end). a/d converter output code (at mode (1) register d 5 = 1) the format of an adc digital output is a straight binary. thus, when input a zero reference voltage, the output code is "all 0", and when input a full scale voltage, the output code is "all 1". clock, pipeline delay, digital data output timing the adck input is used for an a/d conversion. the adc input signal is sampled at the falling edge of the adck input and 10-bit parallel data is output at the rising edge of the adck input after 5.5 clocks of pipeline delay. high-z control of adc digital output adc digital outputs become high-z under following conditions : q set the adc output bit to "1". [mode (1) register d 2 = 1] w set the sybyn pin to low. e set the power control bit to "1". [mode (1) register d 0 = 1] msb a/d input digital output code lsb d 9 zero scale 0 : :0 :1 : full scale 11 0 1 0 d 0 1 0 1 0 d 1 1 0 1 0 d 2 1 0 1 0 d 3 1 0 1 0 d 4 1 : 0 1 : 0 d 5 1 0 1 0 d 6 1 0 1 0 d 7 1 0 1 0 d 8 adc data output (coding : straight binary)
IR3Y48A1 13 miscellaneous functions adc direct input (adin mode) the direct input path to the adc or the pga becomes available by register setting. the selectable paths are shown below : 1. function disable (default) [mode (1) register d 5 = 0, d 4 = 0] 2. adin input to the pga [mode (1) register d 5 = 0, d 4 = 1] 3. adin input to the adc [mode (1) register d 5 = 1, d 4 = don't care] at the adin mode, the blk, shd and shr inputs are ignored. the operation at adc direct input is shown below. thus, the clamped level at the adclp timing becomes a reference (clpcap at the figure below), and the adin input dynamic range is +1.0 v (typ.) from the reference level. adin (n) n C 8 n C 7 n C 6 n C 5 n C 4 n C 3 n C 2 n C 1 n (n + 1) (n + 2) adck (when adck is inverted, signal (n) is sampled by this edge.) adclp black cancel & clamp do 0 -do 9 adin signal processing (pga input) note : this figure shows the timing when an outck input function is disabled (mode (1) d 8 = 0). when it is enabled (d 8 = 1), the data is output at the rising (d 7 = 0) or the falling (d 7 = 1) edge of the outck input. when adclp input is low, both black level cancel and clamp are active at the pga input mode, and only the clamp is active at adc input mode. clamp on full scale clpcap + 1.0 v adc dynamic range = 1.0 vp-p clpcap zero scale adin adclp adin signal input level
IR3Y48A1 14 power down mode the power down mode can be set either by register setting or stbyn pin. if one of them is set, the IR3Y48A1 powers down. ("or" logic) monitor output by setting the register [mode (2) register d 1 & d 0 ], the signal from monout is selectable. alternatives are off, cds output, pga output, or refin/ ccdin output. note that the gain of the monout pin is fixed to 0 db regardless the setting of gain control register when the cds output is selected. the output level of monout is shown below. the monout level becomes v com at zero reference level. the signals are output in reverse for the ccd input. ccd monout v 0 = no signal v 0 = no signal level monitor reference level = v com v 1 v 1 ' v 2 v 2 ' v 3 v 3 ' monitor output level polarity inversion the following input polarities can be inverted by register setting : q adck (a/d converter sampling clock) [mode (1) register d 6 ] w shr and shd (cds sampling clock) [mode (2) register d 3 & d 2 ] e blk, obp, ccdclp and adclp (enable controls) [mode (2) register d 3 & d 2 ]
IR3Y48A1 15 serial interface write control power control usually, make the power control register (mode (1) register d 3 ) "1" to select low power mode. the default setting of this register is "1". data output clock the adck input or the outck input is selectable as an adc data output clock. general notice for power supply it is recommended to supply power to both av dd and dv dd from a single regulator. (keep the absolute maximum rating; dv dd (av dd + 0.3 v) even at the power-up or the power- down sequence.) refer to "application circuit example" for power supply decouplings. serial interface circuit the internal registers of IR3Y48A1 are controlled by the 3-wire serial interface. the data is a 16-bit- length serial data that consists of a 2-bit operation code, a 4-bit address, and a 10-bit data. the each bit is fetched at the rising edge of the sck input and the data is executed at the rising edge of the csn input. when not access, make the csn input high. it is prohibited to write to a non-defined address. when a data length is below 16-bit, the data is not executed. 0 1 2 3 4 5 6 7 8 9 101112131415 csn sck sdata op code address data o 0 o 1 a 0 a 1 a 2 a 3 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 op code is always ineffective (don't care).
IR3Y48A1 16 registers the IR3Y48A1 has 10-bit x 7 registers to control its operations. two of the seven registers are used for the lsi testing. all registers are write only. the serial registers are written by the serial interface. register map a 3 r/w address register name major functions [data] a 2 a 1 a 0 0 0 1 adc code at black level (1 lsb step) black level 0 w 1 1 0 pga gain pga gain 0 w 0 1 0 cds gain control/black loop gain boost/boost period mode (3)/cds gain 0 w 1 0 0 clamp current/adin clamp/clamp target/ s/h, enable logic/monitor selection mode (2) 0 w 0 0 0 dout timing control/outck polarity/adck polarity/adin connection/power control/adc output/black level reset/power down mode (1) 0 w w 1 test (1) test mode (1) (adin coupling mode) 000 1 0 0 test mode (2) test (2) 1 w 1. register name mode (1) 2. register address [write] 3. register bit assignment a 3 a 2 a 1 a 0 0 0 0 0 d 9 power control adin connection adck polarity outck polarity dout timing control x0 d 0 0 d 1 0 d 2 0 d 3 0 d 4 0 d 5 0 d 6 0 d 7 0 d 8 adc output <-> <----> <-> <-> <-> functions <-> default <-> power down <-> black level reset
IR3Y48A1 17 4. register operations adc output power control outck polarity dout changes at outck rising edge adck clock inversion adin signal to pga not recommended normal operation [adc data output] dout synchronizes to adck controls operations note d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 9 dout timing control 1 dout synchronizes to outck 1 dout changes at outck falling edge normal operation as timing chart adin function off adin signal to adc 2 low power 3 adc output high-z [or logic of stbyn] notes : 1. dout edge control is effective when d 8 = 1 (dout synchronizes to outck). 2. power control bit (d 3 ) must be "1" to operate as specified value. the default value is "1" (low power). 3. adc output is set to high impedance if one of the following case is true. case 1 : set "adc output" bit to "1". case 2 : set stbyn pin to low. case 3 : set "power down" bit to "1". 4. black level integral cap [obcap] is discharged if the following case is true. case 1 : set "black level reset" bit to "1". case 2 : set resetn pin to low. power down [or logic of stbyn] power down normal operation black level reset [or logic of resetn] 4 black level reset normal operation adck polarity adin connection 0 1 0 1 0 1 0 0 1 0 1 x 0 1 0 1 0 1 0 1 x : don't care
IR3Y48A1 18 1. register name mode (2) 2. register address [write] 3. register bit assignment a 3 a 2 a 1 a 0 1 0 0 0 d 9 monitor selection x : don't care s/h, enable logic clamp target adin clamp clamp current x0 d 0 0 d 1 0 d 2 0 d 3 0 d 4 0 d 5 0 d 6 0 d 7 x d 8 <----> <----> <----> <-> <-> functions default 4. register operations s/h, enable logic adin clamp clamp operation active for adin clamp refin only clamp off normal operation as timing chart enable control polarity inversion normal clamp (50 a) controls operations note d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 9 clamp current 2 fast clamp (100 a) no clamp for adin normal mode [clamp both refin and ccdin] clamp ccdin only 1 s/h control polarity inversion both of s/h and enable inversion output refin and ccdin (for calibration) pga output monitor 4 cds signal to monitor 3 monitor selection monitor off clamp target 0 1 0 1 00 01 10 11 00 01 10 11 00 01 10 11 notes : 1. the s/h signals are shr and shd. 2. the enable controls are blk, obp, ccdclp, and adclp. 3. at this mode, monitor output gain = 0 db regardless of cds gain. 4. at this mode, monitor output depends on cds gain.
IR3Y48A1 19 1. register name mode (3) 2. register address [write] 3. register bit assignment x : don't care a 3 a 2 a 1 a 0 0 1 0 0 d 9 black loop gain boost x0 d 0 0 d 1 0 d 2 0 d 3 0 d 4 0 d 5 x d 6 x d 7 x d 8 <----> cds gain control default 4. register operations controls operations note cds gain = 0 db cds gain control d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 00 1 0 1 0 1 1 boost control on always high gain always low gain 1 2 3 1, 3 1, 3 1, 3 1, 3 1, 3 1, 3 1, 3 boost period <-> <-------> black loop gain boost cds gain = +6.02 db cds gain = +12.04 db cds gain = C1.94 db boost period 0 1 000 001 010 011 100 101 110 111 high gain for 1 obp pulse high gain for 2 obp pulses high gain for 3 obp pulses high gain for 4 obp pulses high gain for 5 obp pulses high gain for 6 obp pulses high gain for 7 obp pulses notes : 1. black loop settling gain is boosted [speed up] for defined period. gain is boosted n obp pulse(s) after rising edge of csn [sio data write]. boosted period n (1 to 7 pulses) is determined by "boost period" (d 2 ...d 0 ). after n obp pulse(s), black loop gain returns automatically to low gain. 2. black loop settling is always high gain [boosted]. 3. "boost period" register is effective only when d 3 = 1.
IR3Y48A1 20 1. register name pga gain 2. register address [write] 3. register bit assignment a 3 a 2 a 1 a 0 1 1 0 0 d 9 pga gain x0 d 0 0 d 1 0 d 2 0 d 3 0 d 4 0 d 5 0 d 6 0 d 7 0 d 8 functions default <------------------------------------> x : don't care 4. register operations 0 0 10 00 128 0 80 6.020 1 0 010000 65 0 41 3.057 1 1 011111 127 0 7f 5.973 1 0 100000 129 0 81 6.067 0 0 010000 64 0 40 3.010 1 1 001111 63 0 3f 2.963 0 1 001111 62 0 3e 2.916 0 0 000001 4 0 4 0.188 1 1 000000 3 0 3 0.141 0 1 000000 2 0 2 0.094 1 0 000000 1 0 1 0.047 0 0 000000 0 0 0 0.000 controls decimal d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 9 pga gain hex pga gain (db) 9.030 c0 0 192 0 0 0 0 1 100 0 0 010000 320 1 140 15.050 1 0 000000 257 1 101 12.087 0 0 000000 256 1 100 12.040 1 1 111111 255 0 ff 11.993 00 24.033 1ff 1 511 1 1 1 1 1 111 23.986 1fe 1 510 1 1 1 1 1 110 21.070 1c0 1 448 0 0 0 0 1 100 18.107 181 1 385 0 0 0 0 0 101 18.060 180 1 384 0 0 0 0 0 100 18.013 17f 1 383 1 1 1 1 1 011
IR3Y48A1 21 note : 1. codes 1 to 15 are available but not recommended. black calibration period is specified under 15 < code < 128. 1. register name black level 2. register address [write] a 3 a 2 a 1 a 0 0 0 1 0 3. register bit assignment 4. register operations d 9 black level x0 d 0 0 d 1 0 d 2 0 d 3 0 d 4 0 d 5 1 d 6 x d 7 x d 8 functions default <-----------------------------> x : don't care 0 0 01000 32 20 0 0 10000 64 40 0 0 11111 124 7c 1 1 00100 19 13 0 1 00100 18 12 1 0 0 0 17 11 0 0 00100 16 10 1 1 00011 15 f 1 1 1 0 00000 1 1 1 0 0 0 0 0 0 0 forbidden forbidden operations [adc code : binary] black code b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 9 black level note 7e 126 1 1 1 1 110 1 1 11111 127 7f 1 0 11111 125 7d 1 0 0 decimal hex
IR3Y48A1 22 4. register operations the test register (d 6 ) is for the ac coupled adin input mode. at this mode, the dc bias becomes the v com voltage and no clamp signals are required. connect a 50 k$ resistor between the adin (pin 14) and clpcap (pin 13), and input the signal to the adin pin via a capacitor. 0 normal operation controls operations d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 9 adin test mode v com centered adin for ac coupling 1 1. register name test (1) 2. register address [write] a 3 a 2 a 1 a 0 0 0 0 1 3. register bit assignment x : don't care note : d 5 to d 0 must always be "0". d 9 adin test mode x0 d 0 0 d 1 0 d 2 0 d 3 0 d 4 0 d 5 0 d 6 x d 7 x d 8 functions default <-> 1. register name test (2) 2. register address [write] a 3 a 2 a 1 a 0 1 0 0 1 3. register bit assignment x : don't care note : d 4 to d 0 must always be "0". d 9 test modes x0 d 0 0 d 1 0 d 2 0 d 3 0 d 4 x d 5 x d 6 x d 7 x d 8 functions default <------------------->
IR3Y48A1 23 absolute maximum ratings (av ss = dv ss = 0 v, all voltages are with respect to gnd.) parameter symbol conditions unit power supply voltage av dd v C0.3 to +4.5 rating dv dd C0.3 to +4.5 or av dd + 0.3 v ma 10 except power supply pins i in 0.3 v dv dd C av dd v dlt voltage difference analog input voltage v ina v av ss C 0.3 to av dd + 0.3 av ss C 0.3 to av dd + 0.3 v v inl digital input voltage (input pin) v digital input voltage (output pin) av ss C 0.3 to av dd + 0.3 ?c v onl operating temperature ?c t opr storage temperature t stg C40 to +125 C30 to +85 2 1 note input current recommended operating conditions (av ss = dv ss = 0 v, all voltages are with respect to gnd.) parameter symbol conditions typ. supply voltage at start-up, turn on av dd before (or at the same time as) turning on dv dd . 3.0 2.7 min. v unit 3.6 max. av dd analog digital output dv dd av dd v 2.7 3.0 notes : 1. the higher voltage of 4.5 v or av dd + 0.3 v specifies maximum value of dv dd absolute maximum rating. 2. the v onl limits the excess voltage applied to digital output pins. warning : operation at or beyond these limits may result in permanent damage to the device. normal operating specifications are not guaranteed at these extremes. p d derating ratio t a > 25?c mw/?c 4.5 power consumption p d t a 25?c mw 570 electrical characteristics supply current (note 1) (t a = +25?c, av dd = dv dd = 3.0 v) notes : 1. specified at a 4.7 k$ aiset resistance. use a high precision resistor because it influences the supply current. 2. specified when the monitor function is off. 3. measured when connecting 10 pf capacitors between the do 0 to do 9 pins and gnd, and inputting full scale of 1 mhz sine wave to the adc. 4. measured under no analog input and with clock fixed at low. parameter symbol conditions typ. supply current at normal operation 28 min. ma unit 31 max. i a analog digital i d 7ma 5 fs = 18 mhz note 2 supply current at monitor active i pe fs = 18 mhz 3 34 ma 30 ma 0.1 4 i pd supply current at power down 2, 3
IR3Y48A1 24 notes : 1. the signal dynamic range is below the clamp voltage at the ccdin input, and it is above the one at the adin input. the v icds is applied at the 0 db gain. when the gain is below 0 db, v icds is 1.25 vp-p (typ.). 2. measured at the monout pin. the noise bandwidth is 100 khz to 5 mhz. 3. the bandwidth from the ccdin/refin to the adc. this is defined as the settling time of the adc when the full scale C 1 db step input is inputted and the gain is 0 db. 4. the time that is needed to settle the average value within 1 lsb for the set code when the pga gain is changed. (the obcap capacitor is 0.1 f.) the value of the obcap capacitor determines the bandwidth of the black calibration loop. the loop gain is also affected by the operation frequency. therefore the maximum frequency that is needed to settle within a limited time and the minimum frequency that is needed to avoid the undesirable oscillation are defined corresponding with the external capacitance. refer to the table below to select the capacitance. 5. the maximum calibratable offset means the difference of the ccdin reference level and the set data at the obp period. analog specifications (unless otherwise specified, av dd = dv dd = 3.0 v, t a = +25?c, signal frequency f in = 1 mhz, signal level = full scale C 1 db.) the current direction flowing into the pin is positive direction. cds & clamp circuits (sampling frequency f s = 18 mhz) parameter symbol conditions typ. min. unit max. note analog input range v icds ccdin input vp-p 1.1 50 v rms 1 at fs = 18 mhz ni equivalent input noise v iai adin input at max. gain at min. gain 1.0 200 vp-p v rms input capacitance c in ccdin, adin & refin pf 15 cbw 1 pixel 3 2 input bandwidth clamp voltage v 1.95 1.8 1.65 ccdin input v clpcap adin input 1.3 v black calibration time 4 pixel 200 t bkcal 1.15 1.45 v bkcal 200 mv 5 maximum calibratable offset voltage minimum frequency (mhz) maximum frequency (mhz) obcap capacitance (f) 4 8 within 200 pixels 0.1 0.15 11 0.068 0.33 3 up to 18 up to 18 up to 14 up to 6 up to 10 up to 18 up to 18 up to 18 within 400 pixels
IR3Y48A1 25 notes : 1. measured at the digital output pins (do 0 to do 9 ). when the input voltage is 1.0 vp-p and adc output is the full scale, the absolute gain is defined as a 0 db. the relative gain is the relative value from the absolute gain. the gain monotonicity is guaranteed except least significant bit. 2. measured at the digital output pins (do 0 to do 9 ). parameter gain symbol conditions typ. min. unit max. note cds gain g mnn absolute gain 0.1 db C1.9 C0.9 1 g (1) 5.52 6.02 6.52 db select 0 db select 6.02 db select 12.04 db db 12.04 12.04 11.54 g (2) pga input g mnna absolute gain 0.7 db C1.3 C0.3 1 g mxna 22.906 23.906 24.906 db minimum gain maximum gain gain step db 0.094 0.047 0 g sta total (cds + pga) gain monotonicity er pa 2 lsb 2 relative gain relative gain parameter symbol conditions typ. min. unit max. note resolution res 10 bits s/n sn db 58 1 0.6 lsb 1.0 fs = 18 mhz dnl differential nonlinearity 16 lsb 127 c cal adc output black level calibration code 1 lsb st cal calibration code resolution 0.85 0.75 v 0.95 v rn v ref voltage (negative) 1.35 1.25 v 1.45 v rp v ref voltage (positive) 1.1 1.0 v 1.2 v com adc common voltage 56 db snd s/(n + d) a/d converter circuit (f s = 18 mhz, input signals to adin.) notes : 1. non missing code is guaranteed. 2. black calibration period (t bkcal ) is specified when the c cal is from 16 to 127 lsb. although black level codes of 1 to 15 could be set, t bkcal is not guaranteed for these codes. 1 127 lsb 2 g (3) C2.44 C1.94 C1.44 db select C1.94 db
IR3Y48A1 26 switching characteristics (av dd , dv dd = 2.7 to 3.6 v, av ss , dv ss = 0 v, t a = C30 to +85?c, c l < 10 pf) parameter symbol conditions typ. min. unit max. conversion frequency f s 18 mhz 0.5 outck hold outck setup 0 ns t suoc enable pulse hold10 ns t he sampling pulse non-overlap 10 ns t sue data pulse hold5 ns t hd shd sampling aperture ns 4 t dd shr sampling aperture ns 4 t dr shd pulse width 11 ns t wd shr pulse width 11 ns t wr clock high period23 ns t h clock low period23 ns t l clock fall time ns 2 (70% / 30%) av dd , dv dd t f ns 2 (30% / 70%) av dd , dv dd t r clock cycle time 55 ns t cyc clock rise time note data pulse setup 2 ns t sud 1 t sp ns 1 enable pulse setup t hoc ns 10 t dld active / high-z ns 20 3 state disable delay 3 state enable delay adc output data delay note : 1. when shd? is earlier than adck?, assumed positive. (in the above table, shd? must be earlier at least 2 ns than adck?.) t dle high-z / active ns 20 t dl1 ns 2 t dl2 35 ns
IR3Y48A1 27 timing chart ccd shr shd do 0 -do 9 blk obp ccdclp adclp adck outck reference sampling data sampling t he t sue t dr t dd t sud t sp t hd t wr t wd t dl t cyc t h t l t hoc t suoc this chart is shown when the mode (1) d 8 bit is set to "1", and an external clock is input to the outck pin. when setting d 8 bit to "0", the adck is used as outck.
IR3Y48A1 28 adck inversion adck rising edge n + 1 n sampling point adc input adck outck outck timing t hoc t suoc adin : adc direct input adck adc input outck digital output falling edge 0.7 av dd 0.3 av dd 0.7 av dd 0.3 av dd n n + 1 n + 4 n + 5 n + 6 sampling point n C 6 n C 5 t dl n C 2 n C 1 n n C 2 n C 1 n ad conversion timing (at adin (adc) input [mode (1) register d 5 = 1]) these figures are shown when the mode (1) d 8 bit is set to "1", and an external clock is input to the outck pin. when setting d 8 bit to "0", the adck is used as outck.
IR3Y48A1 29 t f t l t h 0.7av dd 0.3av dd t cyc t r adck clock waveform note : at default condition in adin mode, data are sampled at the falling edge of the adck clock, and are output at the rising edge of the outck clock. when the data are sampled and are output at the falling edge of the adck clock, set adck polarity register to "1". (the upper figure on the previous page shows default timing, and the lower left figure on the previous page shows inverted timing.) delay from data sampling to data output adck normal : at [mode (1) register d 6 = 0] 5.5 clk delay adck inversion : at [mode (1) register d 6 = 1] 6.0 clk delay in adin input mode, the above-mentioned register setting is available. at adin (pga) input [mode (1) register d 5 = 0 & d 4 = 1] digital data output is delayed from above timing by 2 clk.
IR3Y48A1 30 parameter symbol conditions typ. min. unit max. sck clock frequency s cyc 10 mhz number of serial data 16 pcs snum sck, csn fall time ns 6 70% / 30% s f sck, csn rise time ns 6 30% / 70% s r data hold time 20 ns s h data setup time 20 ns s su 40 ns s hi 40 ns s lo sck clock high level width sck clock low level width control interface timing (av dd , dv dd = 2.7 to 3.6 v, av ss , dv ss = 0 v, t a = C30 to +85?c) s su o 0 o 1 a 0 snum d 8 d 9 s cyc s lo s hi s h s su s h csn sck sdata 50%dv dd 50%dv dd 50%dv dd serial i/f timing input "high" voltage v 0.7av dd v ih1 parameter symbol conditions typ. min. unit max. a 10 a 10 v 0.3av dd high-z leakage current i oz input "high" leakage current i likg v il1 input "low" voltage 1 note output "high" voltage 0.7dv dd v i oh = C1 ma v oh output "low" voltage v 0.3dv dd i ol = 1 ma v ol digital dc characteristics (av dd , dv dd = 2.7 to 3.6 v, av ss , dv ss = 0 v, t a = C30 to +85?c, measured as a dc characteristics.) note : 1. applied to shd, shr, adck, blk, obp, ccdclp, adclp, csn, sck, sdata, resetn, stbyn and outck.
IR3Y48A1 31 data output sequence pixel data readout sequence (1) : conversion start pixel data readout sequence (2) : conversion end ccd black level code 0123 012345678 shr shd adck outck blk do 0 -do 9 ccd shr shd adck outck blk do 0 -do 9 n black level code n C 1 (n C 1) (n) n C 2 n C 3 n C 4 n C 5 n C 6 n C 7 n C 8
IR3Y48A1 32 clock timing variations by register setting the variations of clock timings when it is inverted by register settings. 1. no inversion (mode (1) register d 6 = 0, mode (2) register d 2 = 0; default) (upper figure) 2. adck inversion (mode (1) register d 6 = 1, mode (2) register d 2 = 0) (lower figure) ccd shr shd adck outck do 0 -do 9 ccd shr shd adck outck do 0 -do 9 pulse control (default : no inversion) pulse control (adck inversion)
IR3Y48A1 33 3. shr & shd inversion (mode (1) register d 6 = 0, mode (2) register d 2 = 1) (upper figure) 4. adck, shr & shd inversion (mode (1) register d 6 = 1, mode (2) register d 2 = 1) (lower figure) ccd shr shd adck outck do 0 -do 9 ccd shr shd adck outck do 0 -do 9 pulse control (shr & shd inversion) pulse control (adck, shr & shd inversion)
IR3Y48A1 34 application circuit example the following schematic is the reference circuit for system design. optimize capacitance and resistance according to the system environment. monitor adin sampling pulse ccd 3 v (typ.) 10 f digital out 0.1 f + 36 35 34 33 32 31 30 29 28 27 25 123456789101112 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 do 0 do 1 do 2 do 3 do 4 dv ss dv dd do 5 do 6 do 7 do 8 do 9 shd shr adck nc av ss1 av dd1 aiset nc monout obcap clpcap adin outck resetn dout clock chip control chip control power down av dd3 av ss3 stbyn csn sdata sck obp ccdclp blk adclp 26 refin ccdin v com av ss2 av ss2 av dd2 av dd2 v rp v rn nc av dd4 nc analog digital 0.1 f sio control pulse 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 4.7 k$ 0.1 f top view

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